Software-defined process-near-memory architecture using 3D hybrid bonding integration

With the unprecedented explosive growing amount of global data, the development of computing chips, which encounter bottlenecks such as power wall and memory wall, cannot satisfy the demanding requirement. This work proposes a software-defined process-near-memory (SDPNM) computing architecture implemented using 3D hybrid bonding integration. The software-defined chip architecture, featuring spatial computations and dynamic reconfiguration, innovates in a top-down manner to achieve high energy efficiency while maintaining flexibility after fabrication. The process-near-memory integration further advances the SDNPM chip in a bottom-up way to reduce the energy consumption of data movement while improving the bandwidth. Utilizing a relatively mature fabrication and bonding process can result in feasible solutions for both data-intensive and compute-intensive applications including digital signal processing and artificial intelligence. The logic die is fabricated in the SMIC 40 nm process and the DRAM die is fabricated in the PSMC 25 nm process. The hybrid bonding is implemented by XMC. The experimental results show that the energy efficiency of the proposed SDPNM chip is 33.1× better than the state-of-the-art FPGA ranging from 8.2× to 104.1×.