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<p>For 5G mmWave systems, the hybrid beamforming (HB) architecture has received a lot of attention. Because there are significantly fewer RF links than antennas, it lowers the hardware complexity. Nevertheless, asymptotic complexity analysis has been the main focus of the majority of previous studies. This work proposes a hybrid beamforming architecture that combines parallel acceleration and randomized SVD for wideband mmWave multiple input multiple output (MIMO) systems with reduced hardware usage. Also, the singular value decomposition (SVD) architecture incorporates Extreme Data Sharing ranking (EDSR) to maximize the data and minimize the bandwidth requirement. The proposed research undergoes three main phases. Phase I utilizes a sparse channel estimation (SparseCE) core for channel state information (CSI) estimation to evaluate beamforming matrices. In phase II, the SVD with parallel architecture is developed to attain the singular vectors by performing interference calculation and beamforming. By utilizing the obtained singular vectors, the final digital beamforming matrices are constructed in the third stage. The proposed design is implemented in the Xilinx platform, and the performance measures, such as execution time and throughput, are examined and compared with existing beamforming architectures. Also, the FPGA analysis in terms of register transfer level (RTL) schematic view, simulation waveform, and device utilization summary is conducted to show the robustness of the proposed study.</p>

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A FPGA-Enabled Hybrid Beamformer for 5G Millimeter Wave Massive MIMO System

  • 期刊论文

  • 发表日期：

    2026年7月7日

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  • Spoorthi S P,
  • Bharathi S H

摘要

For 5G mmWave systems, the hybrid beamforming (HB) architecture has received a lot of attention. Because there are significantly fewer RF links than antennas, it lowers the hardware complexity. Nevertheless, asymptotic complexity analysis has been the main focus of the majority of previous studies. This work proposes a hybrid beamforming architecture that combines parallel acceleration and randomized SVD for wideband mmWave multiple input multiple output (MIMO) systems with reduced hardware usage. Also, the singular value decomposition (SVD) architecture incorporates Extreme Data Sharing ranking (EDSR) to maximize the data and minimize the bandwidth requirement. The proposed research undergoes three main phases. Phase I utilizes a sparse channel estimation (SparseCE) core for channel state information (CSI) estimation to evaluate beamforming matrices. In phase II, the SVD with parallel architecture is developed to attain the singular vectors by performing interference calculation and beamforming. By utilizing the obtained singular vectors, the final digital beamforming matrices are constructed in the third stage. The proposed design is implemented in the Xilinx platform, and the performance measures, such as execution time and throughput, are examined and compared with existing beamforming architectures. Also, the FPGA analysis in terms of register transfer level (RTL) schematic view, simulation waveform, and device utilization summary is conducted to show the robustness of the proposed study.