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<p>Sparse channel estimation plays a critical role in improving the performance of millimeter-wave (mmWave) communication systems, particularly in the context of high-dimensional data and low-latency requirements. To ensure reliable data transmission, accurate channel status information is required due to the significant path loss of wave propagation at such high frequencies. This research proposes a new hardware-friendly sparsity core (SparseCE core) channel estimator for mmWave systems. The proposed channel estimation core consists of three main functional units, namely the Antenna-to-Beamspace Translation (ABT) unit, the Arithmetic optimized unbiased risk estimator based denoising (AoURED) unit, and the Beamspace-to-Antenna Translation (BAT) unit. By leveraging these modules, the SparseCE core achieves significant improvements in hardware efficiency, computational accuracy, and real-time performance. The noisy antenna-domain channel vector was converted into the beamspace domain by the ABT conversion module using a Fast Fourier Transform (FFT) with a CORDIC spinner (FFTCORDIC-Spin). The proposed AoURED model consists of a sort and scan module, and the module is employed with several arithmetic units, namely tree structured magnitude comparator (TreeMC), an Add-one circuit driven Carry Select Adder (AoCSLA), to diminish the complexity of the channel estimation model. The proposed channel estimation core is implemented using Xilinx ISE 14.7 and the MATLAB platform, and several measures are evaluated and compared with existing channel estimation algorithms. Simulation and synthesis results demonstrate that the proposed architecture outperforms conventional implementations in terms of area, power, and latency, making it suitable for real-world deployment in mmWave systems. The proposed algorithm is evaluated using simulation metrics like mean square error (MSE) and bit error rate (BER). Similarly, resource utilization, power, delay, and throughput are used to assess the hardware efficiency of the proposed architecture.</p>

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SparseCE Core: A Sparsity Based Channel Estimation Core Using Arithmetic Optimized Unbiased Risk Estimator for 5G Millimeter Wave Systems

  • 期刊论文

  • 发表日期：

    2026年1月5日

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  • Spoorthi S P,
  • Bharathi S H

摘要

Sparse channel estimation plays a critical role in improving the performance of millimeter-wave (mmWave) communication systems, particularly in the context of high-dimensional data and low-latency requirements. To ensure reliable data transmission, accurate channel status information is required due to the significant path loss of wave propagation at such high frequencies. This research proposes a new hardware-friendly sparsity core (SparseCE core) channel estimator for mmWave systems. The proposed channel estimation core consists of three main functional units, namely the Antenna-to-Beamspace Translation (ABT) unit, the Arithmetic optimized unbiased risk estimator based denoising (AoURED) unit, and the Beamspace-to-Antenna Translation (BAT) unit. By leveraging these modules, the SparseCE core achieves significant improvements in hardware efficiency, computational accuracy, and real-time performance. The noisy antenna-domain channel vector was converted into the beamspace domain by the ABT conversion module using a Fast Fourier Transform (FFT) with a CORDIC spinner (FFTCORDIC-Spin). The proposed AoURED model consists of a sort and scan module, and the module is employed with several arithmetic units, namely tree structured magnitude comparator (TreeMC), an Add-one circuit driven Carry Select Adder (AoCSLA), to diminish the complexity of the channel estimation model. The proposed channel estimation core is implemented using Xilinx ISE 14.7 and the MATLAB platform, and several measures are evaluated and compared with existing channel estimation algorithms. Simulation and synthesis results demonstrate that the proposed architecture outperforms conventional implementations in terms of area, power, and latency, making it suitable for real-world deployment in mmWave systems. The proposed algorithm is evaluated using simulation metrics like mean square error (MSE) and bit error rate (BER). Similarly, resource utilization, power, delay, and throughput are used to assess the hardware efficiency of the proposed architecture.