<p>In this paper, we propose an enhanced orthogonal approximate message passing network (OAMP-Net) algorithm, called intelligent detection with sparse computations (IDSC), to significantly reduce the computational complexity of OAMP-Net for massive multiple-input multiple-output (MIMO) systems. While OAMP-Net delivers excellent detection performance, its practical deployment is limited by the high computational cost arising from frequent matrix inversions. To overcome this challenge, the proposed IDSC algorithm adopts a matrix approximation technique to reduce both the dimension and frequency of matrix inversions, effectively eliminating computationally intensive operations. Simulation results and complexity analysis demonstrate that IDSC achieves detection performance comparable to that of OAMP-Net, while greatly reducing computational overhead. To further validate its practical feasibility, a corresponding VLSI architecture is developed and implemented using the TSMC 90-nm CMOS process.</p>

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Intelligent Detection with Sparse Computations for Massive MIMO Systems

  • Mao-Hsu Yen,
  • Hoang-Yang Lu,
  • Hsin Chen,
  • Chia-Hsun Li

摘要

In this paper, we propose an enhanced orthogonal approximate message passing network (OAMP-Net) algorithm, called intelligent detection with sparse computations (IDSC), to significantly reduce the computational complexity of OAMP-Net for massive multiple-input multiple-output (MIMO) systems. While OAMP-Net delivers excellent detection performance, its practical deployment is limited by the high computational cost arising from frequent matrix inversions. To overcome this challenge, the proposed IDSC algorithm adopts a matrix approximation technique to reduce both the dimension and frequency of matrix inversions, effectively eliminating computationally intensive operations. Simulation results and complexity analysis demonstrate that IDSC achieves detection performance comparable to that of OAMP-Net, while greatly reducing computational overhead. To further validate its practical feasibility, a corresponding VLSI architecture is developed and implemented using the TSMC 90-nm CMOS process.