Optimized Design of Low Power 90 nm CMOS Low Noise Amplifier for 60 GHz Applications

Millimeter wave technology attracts a lot of attention towards 60 GHz applications. Due to advantage of continuous scaling of CMOS technology and speed of transistors, 90 nm CMOS technology is selected for designing the circuits. In this paper, broadband low power low noise amplifier (LNA) is designed using 90 nm CMOS process at the operating range of 55 GHz to 67 GHz. Inductively degenerated cascode two stage LNA is designed to achieve low power, high gain and good return loss. Optimization techniques take an advantage to optimize the parameters in analog circuits within a short period of time. Such optimization algorithms such as genetic, random, hybrid, Quasi Newton, random and simulated annealing are used to optimize the designed LNA parameters. The designed LNA provides 27.9 dB gain, -18.7 dB return loss, 1.92 dB noise figure, 5.56 mW power consumption and FoM of 5.45. Optimization algorithms provide better FOM while comparing the designed LNA without optimization. Hybrid algorithm produces high FOM of 48 when compared with other algorithms.