High-Speed and Low-Power Recursive Rounding Based Approximate Multipliers for Error-Resilience Applications

In error-resilience applications, Approximate Multipliers (AMs) play an essential role, having a trade-off between design metrics (DM) and error metrics (EM). Thus, rounding and recursive-based AMs is developed in this paper in order to enhance both DM and EM. Initially, the process entails selecting the least significant and greater significant bits from the n-bit input operand in the n/2-bit stage. These selected bits undergo rounding to the nearest power of two within the architecture of the proposed AMs. Subsequently, the final output multiplication product is derived through a combination of rounding, adders, and shifters. To evaluate the efficacy of this approach, all proposed and prior AMs are implemented in Verilog Code, covering input sizes extending from 8 to 32 bits. These implementations are then synthesized with the Cadence RTL compiler and simulated using both MATLAB and Vivado for image smoothing filter (ISF) applications. Additionally, the DM and EM values of the proposed AMs provide improvement in contrast to prior AMs. Furthermore, the proposed AMs offer an average delay reduction of 21.35% and a 40% reduction in power consumption compared to previous AMs. Moreover, when integrated into the ISF, the proposed AMs exhibit better maximal peak signal-to-noise ratio and structural similarity-index metric compared to existing alternatives, rendering them well-suited for Error- Resilience and energy efficient applications.