Performance Optimization of SAR ADC using Dynamic Controlled Comparator at 45 nm Technology for Biomedical and IoT Applications

The Emerging biomedical applications such as electrocardiography, electroencephalogram, wireless implantable devices have required optimized power-based SAR ADC in them to reduce package cost and to extend battery life. In view of power optimized SAR ADC, a dynamic controlled comparator with novel static power reduction logic incorporated with common mode kickback noise reduction technique is designed at 45 nm technology in CADENCE Virtuoso in this paper. Designed comparator is analyzed in terms of performance parameters; static power dissipation, transient power dissipation, maximum sampling rate, offset voltage and delay. Simulation and behaviour modeling analyses of proposed dynamic comparator has resulted in five times reduction in static power dissipation along with optimization of transient power and sampling rate as well compared to previously available double tail dynamic comparator. Moreover, it has been mentioned that proposed dynamic comparator is dissipating 2.36 pW of static power and 3.59 nW of transient power with sampling rate of 240 KS/s at 0.5 V. Further, the kickback noise of proposed design is limited to 4.7 mV with maximum delay of 124 ps. Finally, the novel outcomes of proposed comparator are the optimization in required parameters such as power, delay, offset voltage and kickback noise for biomedical applications as compared to double tail dynamic comparator. The proposed consideration for SAR ADC can become a backbone for low power biomedical applications.