A Hybrid Message-level Modeling Approach for Fast Yet Accurate Simulation of Multiprocessor Shared Bus Effects on Data Flow Applications Execution
摘要
Fast yet accurate performance and timing prediction of complex parallel data flow applications on multiprocessor systems remains a challenging discipline. The main reason is that the applications contain numerous degrees of parallelism (task, pipeline, data) but they necessitate sharing resources, such as communication buses and memories, within execution platforms. Executing such applications on resource-limited platforms leads to timing interferences that are difficult to accurately express in pure analytical approaches or to excessive simulation duration for cycle-accurate models. In this work, we propose a message-level communication model for fast yet accurate performance prediction for data flow applications executed on MPSoCs with shared memories and buses. This approach combines a high level executable model of the communication infrastructure with a formal description of the synchronization instants related to low-level communication mechanisms. This combination significantly reduces the number of simulation events while still accurately predicting the effects of contention at shared resources. We evaluated our work against measurements from a real prototype and cycle-accurate performance prediction models on two case-studies from the computer vision domain. We illustrated how the computational complexity of our approach can be adapted to deliver high simulation efficiency. In our experiment, we achieved an average accuracy of