Memory Aware Design Optimisation for High-Level Synthesis

The FPGA environment is traditionally exotic to high-level software developers, mainly due to the large difference in the development methodologies. This can be mitigated through High-Level Synthesis (HLS) tools. By incorporating complex models and code analyses, these tools allow the use of software languages as input for FPGA designs. This paper presents a Design Space Exploration (DSE) approach that uses an estimator named Lina. This approach iterates over hundreds/thousands of combinations of HLS compiler directives in search for the best one, while avoiding HLS runs. Lina approximates the performance and resource usage that the HLS compiler would reach for each combination of directives. It uses simpler models, and as such it runs generally faster than HLS compilation. This version of Lina has an off-chip memory model, allowing the estimation of off-chip memory accesses considering several aspects such as burst detection, data packing, and effect of other compiler directives. For a simple convolution kernel with off-chip accesses, explorations using Lina correctly inferred all but one of the compiler directives when searching the solution with best performance. The best points given by the approach were always in the top-10, reaching at least \(720\times \) $720\times$ speed-up without considering start/end data transfers. Explorations of 4 kernels from Parboil benchmark are also presented. Although there is still significant non-optimised data transfer overheads, speed-ups were reached in all kernels.