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<p>A compact and efficient hardware architecture is proposed for Ed25519-based Elliptic Curve Cryptography (ECC), targeting resource-constrained embedded and IoT devices. The design adopts a four-level modular hierarchy comprising signature control elliptic curve operations, finite-field arithmetic, and binary computation layers. Innovations include a dual-path modular adder-subtractor for parallel execution, a Binary Euclidean Algorithm (BEA) based modular inversion unit, and optimized point operations requiring limited multiplications and squarings for point doubling, and point addition. Implemented on a Xilinx Artix-7 FPGA, the scalar multiplication unit requires 20,360 LUTs and 9,772 flip-flops, operating at 135.5 MHz with a low latency of 9.45uS. The architecture achieves strong area-speed trade-offs. Future enhancements will explore dynamic power reduction and ASIC integration.</p>

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Design and FPGA implementation of an area-efficient elliptic curve cryptographic processor

  • 期刊论文

  • 发表日期：

    2026年4月18日

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  • Bukke Chandrababu Naik,
  • B. Naresh Kumar Reddy

摘要

A compact and efficient hardware architecture is proposed for Ed25519-based Elliptic Curve Cryptography (ECC), targeting resource-constrained embedded and IoT devices. The design adopts a four-level modular hierarchy comprising signature control elliptic curve operations, finite-field arithmetic, and binary computation layers. Innovations include a dual-path modular adder-subtractor for parallel execution, a Binary Euclidean Algorithm (BEA) based modular inversion unit, and optimized point operations requiring limited multiplications and squarings for point doubling, and point addition. Implemented on a Xilinx Artix-7 FPGA, the scalar multiplication unit requires 20,360 LUTs and 9,772 flip-flops, operating at 135.5 MHz with a low latency of 9.45uS. The architecture achieves strong area-speed trade-offs. Future enhancements will explore dynamic power reduction and ASIC integration.