<p>Network-on-chip (NoC) provides a scalable communication framework for next-generation many-core chips by decoupling computation from communication. On-chip radiation-induced transient faults, often caused by charged alpha particles emitted from solder balls, pose a significant threat to NoC reliability, particularly in routers. Routers typically occupy up to 75% of the NoC area and are therefore highly vulnerable to faults, which may lead to packet loss, increased latency, or misrouting. To address these challenges, this paper introduces CoST-HNoC, a fault-tolerant routing scheme specifically designed for hypercube-based NoCs. The proposed framework incorporates a comprehensive fault model that characterizes fault scenarios based on both the number of faults and their spatial distribution. Evaluation results, compared with E-Cube routing, demonstrate maximum reliability improvement factors of 17.65, 70.92, and 92.63 times, as well as an average increase in NoC lifetime of 224.75% across the evaluated failure rate scenarios. CoST-HNoC was simulated using the NS-2 standard simulator. A variety of traffic patterns and a comprehensive fault injection methodology covering different fault distributions were incorporated into the simulation. The simulation results were analyzed using the AWK tool, and the outcomes validate the analytical results.</p>