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<p>This work focuses on the acceleration of deep neural networks (DNNs) for accomplishing computer vision tasks within a resource-constrained environment. Firstly, well-generalized DNNs are developed from a software standpoint for four distinct computer vision datasets. Next, the acceleration is done using a hardware-software co-design approach that implements the software architectures of the model as a reconfigurable programmable logic (PL) and offers room for optimizing trade-offs between memory, power, and speed through high-level synthesis (HLS) based process. The optimized PL is integrated with a general-purpose processing system (PS) and AXI interconnects for realizing an accelerated computing infrastructure. Hence, the computer vision models are optimized through a customized HLS process that incorporates fine-grained optimizations, such as tiled buffers and custom caches, to maximize the reduction of data movement between the PS and PL. In the present work, the accelerated computational architecture is designed with a reconfigurable platform, i.e., ZCU104 Field Programmable Gate Array (FPGA) board, where ZYNQ UltraScale+ MPSoC processing system (PS) is leveraged, and the architecture is tested through the PYNQ overlay process. Experimental results show that co-designed model implementations achieve an accuracy of 95.43–99.99%, a throughput of 252.59–364.50 frames per second (FPS). The power consumption and energy per inference range between 4.44–8.8 W and 12.18–31.20 mJ/image, respectively.</p>

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Hardware acceleration of DL-based computer vision tasks targeting reconfigurable platforms

  • 期刊论文

  • 发表日期：

    2026年7月14日

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  • Abhishek Yadav,
  • Ayush Dixit,
  • Vyom Kumar Gupta,
  • Binod Kumar

摘要

This work focuses on the acceleration of deep neural networks (DNNs) for accomplishing computer vision tasks within a resource-constrained environment. Firstly, well-generalized DNNs are developed from a software standpoint for four distinct computer vision datasets. Next, the acceleration is done using a hardware-software co-design approach that implements the software architectures of the model as a reconfigurable programmable logic (PL) and offers room for optimizing trade-offs between memory, power, and speed through high-level synthesis (HLS) based process. The optimized PL is integrated with a general-purpose processing system (PS) and AXI interconnects for realizing an accelerated computing infrastructure. Hence, the computer vision models are optimized through a customized HLS process that incorporates fine-grained optimizations, such as tiled buffers and custom caches, to maximize the reduction of data movement between the PS and PL. In the present work, the accelerated computational architecture is designed with a reconfigurable platform, i.e., ZCU104 Field Programmable Gate Array (FPGA) board, where ZYNQ UltraScale+ MPSoC processing system (PS) is leveraged, and the architecture is tested through the PYNQ overlay process. Experimental results show that co-designed model implementations achieve an accuracy of 95.43–99.99%, a throughput of 252.59–364.50 frames per second (FPS). The power consumption and energy per inference range between 4.44–8.8 W and 12.18–31.20 mJ/image, respectively.