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<p>Sampled Dense-Dense Matrix Multiplication is a fundamental operation in sparse linear algebra, widely used in graph neural networks and scientific computing. However, accelerating computations on GPUs is challenging due to data sparsity and irregular memory access, which hinder efficient use of Tensor Cores. This paper introduces a Block-Structured Matrix Reordering framework that improves Tensor Core utilization by reorganizing sparse matrices using bi-directional reordering with weighted similarity metrics. We also propose a tile-aware sparse matrix format that improves memory access and task scheduling. To enable adaptive and balanced computation, we employ a dual-path execution strategy: dense matrix blocks are assigned to Tensor Cores, while sparse blocks are handled by CUDA Cores. Experiments on the RTX 4090 demonstrate that our method achieves up to a <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(10.38\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>10.38</mn> <mo>×</mo> </mrow> </math></EquationSource> </InlineEquation> speedup over the best Tensor Core baseline and <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(7.31\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>7.31</mn> <mo>×</mo> </mrow> </math></EquationSource> </InlineEquation> over the best CUDA Core baseline by producing denser block structures and enhancing parallelism.</p>

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Block-structured matrix reordering for efficient SDDMM on tensor cores

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年5月29日

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  • Chengxing Zou,
  • Changwan Hong,
  • Gordon Euhyun Moon,
  • Jinsung Kim

摘要

Sampled Dense-Dense Matrix Multiplication is a fundamental operation in sparse linear algebra, widely used in graph neural networks and scientific computing. However, accelerating computations on GPUs is challenging due to data sparsity and irregular memory access, which hinder efficient use of Tensor Cores. This paper introduces a Block-Structured Matrix Reordering framework that improves Tensor Core utilization by reorganizing sparse matrices using bi-directional reordering with weighted similarity metrics. We also propose a tile-aware sparse matrix format that improves memory access and task scheduling. To enable adaptive and balanced computation, we employ a dual-path execution strategy: dense matrix blocks are assigned to Tensor Cores, while sparse blocks are handled by CUDA Cores. Experiments on the RTX 4090 demonstrate that our method achieves up to a \(10.38\times \) 10.38 × speedup over the best Tensor Core baseline and \(7.31\times \) 7.31 × over the best CUDA Core baseline by producing denser block structures and enhancing parallelism.