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<p>Deploying deep learning models for real-time face mask detection on edge devices requires balancing high accuracy with limited computational resources. While existing studies evaluate model-hardware compatibility, a significant research gap exists in understanding the systemic interplay between peripheral I/O and hardware-accelerated kernels, which often serve as hidden performance throttles. This study completes the system orchestration of a High-Performance Embedded Computing (HPEC) framework to provide a systematic reference for hardware/software selection. We evaluate the performance trade-offs of object detection (YOLOv4) and image classification (Inception V3, MobileNet, VGG16) across standard CPU-based systems and GPU-accelerated edge environments, specifically the NVIDIA Jetson Xavier NX and Raspberry Pi 4 with Intel NCS 2. Experimental results demonstrate that while increasing YOLOv4 resolution to 608 pixels maximizes mAP to 90.01%, it imposes a 14.5 BFLOPS computational penalty. A critical contribution of this work is the quantification of CPU-bound I/O bottlenecks on ARM-based architectures, where inefficient video decoding was found to halve GPU throughput regardless of model efficiency. Furthermore, we establish a 3.8<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> energy efficiency improvement (2.72 J/frame) on the Jetson Xavier NX compared to workstation baselines. These evaluations offer optimized HPEC (High-Performance Embedded Computing) deployment on the Jetson, which is 3.8 <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\times \)</EquationSource> <EquationSource Format="MATHML"><math> <mo>×</mo> </math></EquationSource> </InlineEquation> more efficient than standard workstation-based inference.</p>

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Face mask detection model using deep learning on edge computing

  • 期刊论文

  • 发表日期：

    2026年5月30日

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  • Yu-Wei Chan,
  • Hsin-Ta Chiao,
  • Cenap Oztepe,
  • Endah Kristiani,
  • Chao-Tung Yang

摘要

Deploying deep learning models for real-time face mask detection on edge devices requires balancing high accuracy with limited computational resources. While existing studies evaluate model-hardware compatibility, a significant research gap exists in understanding the systemic interplay between peripheral I/O and hardware-accelerated kernels, which often serve as hidden performance throttles. This study completes the system orchestration of a High-Performance Embedded Computing (HPEC) framework to provide a systematic reference for hardware/software selection. We evaluate the performance trade-offs of object detection (YOLOv4) and image classification (Inception V3, MobileNet, VGG16) across standard CPU-based systems and GPU-accelerated edge environments, specifically the NVIDIA Jetson Xavier NX and Raspberry Pi 4 with Intel NCS 2. Experimental results demonstrate that while increasing YOLOv4 resolution to 608 pixels maximizes mAP to 90.01%, it imposes a 14.5 BFLOPS computational penalty. A critical contribution of this work is the quantification of CPU-bound I/O bottlenecks on ARM-based architectures, where inefficient video decoding was found to halve GPU throughput regardless of model efficiency. Furthermore, we establish a 3.8 \(\times \) × energy efficiency improvement (2.72 J/frame) on the Jetson Xavier NX compared to workstation baselines. These evaluations offer optimized HPEC (High-Performance Embedded Computing) deployment on the Jetson, which is 3.8 \(\times \) × more efficient than standard workstation-based inference.