<p>Network-on-chip (NoC) interconnects underpin system-on-chip designs in high-performance computing. Accurate and fast latency prediction is critical for the performance evaluation of NoCs and scalable design-space exploration. However, most machine learning methods require large amounts of data and lack systematic evaluation across routing algorithms. To address this, we propose a machine learning-based latency prediction model that supports multiple routing algorithms. It employs a progressive cross-scale transfer learning strategy with a co-evolving architecture to maintain accuracy across different networks while substantially reducing training data. Experimental results demonstrate that across four 2D mesh network scales from <InlineEquation ID="IEq1"> <EquationSource Format="TEX">$4\times 4$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>4</mn> <mo>×</mo> <mn>4</mn> </mrow> </math></EquationSource> </InlineEquation> to <InlineEquation ID="IEq2"> <EquationSource Format="TEX">$12\times 12$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>12</mn> <mo>×</mo> <mn>12</mn> </mrow> </math></EquationSource> </InlineEquation>, the model achieves prediction performance (<InlineEquation ID="IEq3"> <EquationSource Format="TEX">$R^2$</EquationSource> <EquationSource Format="MATHML"><math> <msup> <mi>R</mi> <mn>2</mn> </msup> </math></EquationSource> </InlineEquation>) ranging from 98.87% to 99.79%. In <InlineEquation ID="IEq4"> <EquationSource Format="TEX">$8\times 8$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>8</mn> <mo>×</mo> <mn>8</mn> </mrow> </math></EquationSource> </InlineEquation> and <InlineEquation ID="IEq5"> <EquationSource Format="TEX">$12\times 12$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>12</mn> <mo>×</mo> <mn>12</mn> </mrow> </math></EquationSource> </InlineEquation> networks, the model achieves approximately <InlineEquation ID="IEq6"> <EquationSource Format="TEX">$110.7\times $</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>110.7</mn> <mo>×</mo> </mrow> </math></EquationSource> </InlineEquation> and <InlineEquation ID="IEq7"> <EquationSource Format="TEX">$227.5\times $</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>227.5</mn> <mo>×</mo> </mrow> </math></EquationSource> </InlineEquation> end-to-end acceleration compared to Noxim. Moreover, by appending a lightweight predictor–calibrator, we handle hotspot distribution shift without retraining and achieve single-digit errors under leave-one-out cross-validation, as demonstrated on the XY and DyAD routing algorithms.</p>

Latency prediction for network-on-chip architectures via machine learning

期刊论文
发表日期：

2026年4月8日

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Ying Gu,
Weidong Ji,
Jingbo Shao

摘要

Network-on-chip (NoC) interconnects underpin system-on-chip designs in high-performance computing. Accurate and fast latency prediction is critical for the performance evaluation of NoCs and scalable design-space exploration. However, most machine learning methods require large amounts of data and lack systematic evaluation across routing algorithms. To address this, we propose a machine learning-based latency prediction model that supports multiple routing algorithms. It employs a progressive cross-scale transfer learning strategy with a co-evolving architecture to maintain accuracy across different networks while substantially reducing training data. Experimental results demonstrate that across four 2D mesh network scales from $4\times 4$ $4 \times 4$ to $12\times 12$ $12 \times 12$ , the model achieves prediction performance ( $R^2$ $R^{2}$ ) ranging from 98.87% to 99.79%. In $8\times 8$ $8 \times 8$ and $12\times 12$ $12 \times 12$ networks, the model achieves approximately $110.7\times $ $110.7 \times$ and $227.5\times $ $227.5 \times$ end-to-end acceleration compared to Noxim. Moreover, by appending a lightweight predictor–calibrator, we handle hotspot distribution shift without retraining and achieve single-digit errors under leave-one-out cross-validation, as demonstrated on the XY and DyAD routing algorithms.