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<p>This paper proposes a high-efficiency 8-bit architecture for accelerating deep neural networks (DNNs) and addressing key limitations of RRAM-based designs, including high energy overhead, memory bottlenecks, area inefficiency, and limited processing throughput. The proposed design improves computational efficiency through a flexible parallel sliding window mechanism and a novel dataflow strategy that maximizes data reuse via inter-PE sharing and eliminates redundant DRAM accesses. In addition, a parallel weight mapping technique with shared addressing supports efficient parallel computation and coordinated data sharing across processing elements (PEs). These techniques enhance operational intensity and reduce memory bandwidth pressure across all DNN layers, with particularly strong benefits in memory-bound early layers. Evaluations on ResNet-34 demonstrate overall improvements over conventional methods, achieving ~ 2.5 × speed-up and ~ 1.5 × energy efficiency across all layers, together with a 60% reduction in buffer energy consumption. The first layer achieves 70% energy reduction and 60% area reduction, while a 25% memory efficiency improvement is observed across all layers maintaining accuracy above 90%. The design is most effective for layers with input depths under 65, but also benefits deeper layers, making it suitable for resource-constrained systems. Its flexibility enables optimal configuration based on application requirements and hardware constraints.</p>

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Flexible parallel sliding window and data flow methods for deep neural networks on processing-in-memory architectures

  • 期刊论文

  • 发表日期：

    2026年5月5日

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  • Shirin Ghafouri pourKermani,
  • Majid Mohammadi,
  • Mokhtar Mohammadi Ghanatghestani

摘要

This paper proposes a high-efficiency 8-bit architecture for accelerating deep neural networks (DNNs) and addressing key limitations of RRAM-based designs, including high energy overhead, memory bottlenecks, area inefficiency, and limited processing throughput. The proposed design improves computational efficiency through a flexible parallel sliding window mechanism and a novel dataflow strategy that maximizes data reuse via inter-PE sharing and eliminates redundant DRAM accesses. In addition, a parallel weight mapping technique with shared addressing supports efficient parallel computation and coordinated data sharing across processing elements (PEs). These techniques enhance operational intensity and reduce memory bandwidth pressure across all DNN layers, with particularly strong benefits in memory-bound early layers. Evaluations on ResNet-34 demonstrate overall improvements over conventional methods, achieving ~ 2.5 × speed-up and ~ 1.5 × energy efficiency across all layers, together with a 60% reduction in buffer energy consumption. The first layer achieves 70% energy reduction and 60% area reduction, while a 25% memory efficiency improvement is observed across all layers maintaining accuracy above 90%. The design is most effective for layers with input depths under 65, but also benefits deeper layers, making it suitable for resource-constrained systems. Its flexibility enables optimal configuration based on application requirements and hardware constraints.