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<p>Single Instruction Multiple Data (SIMD) extensions play a pivotal role in accelerating computations for both high-performance computing (HPC) and artificial intelligence (AI) workloads. To further exploit these architectures, this study introduces a compiler-based approach that generates parallel code for processors equipped with dual-SIMD extensions via vectorizable loop unrolling. The proposed optimization is implemented in both the GNU Compiler Collection (GCC) and the SWGCC710 compilers as an optional compilation pass that can be activated through a single flag. Performance evaluations conducted on Shenwei and Intel processors–using the SPEC CPU 2006, SPEC CPU 2017, and NAS Parallel Benchmarks (NPB)–demonstrate the effectiveness of the proposed method. Compared with the conventional<Emphasis FontCategory="NonProportional">-O3</Emphasis> optimization level, the technique achieves a geometric mean speedup of 1.031 and up to 1.165 for full applications, whereas kernel loops attain 1.168 on the Shenwei platform. Experiments conducted on Intel systems further confirm the optimization’s portability and its consistent performance improvements across diverse architectures.</p>

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Compiler-based loop unrolling optimization for dual-SIMD extensions

  • 期刊论文

  • 发表日期：

    2026年3月7日

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  • Jinyang Yao,
  • Lili Liu,
  • Xuanyu Fu,
  • Wenbo Liu,
  • Chaowei Zhao,
  • Wei Wu,
  • Zheng Shan

摘要

Single Instruction Multiple Data (SIMD) extensions play a pivotal role in accelerating computations for both high-performance computing (HPC) and artificial intelligence (AI) workloads. To further exploit these architectures, this study introduces a compiler-based approach that generates parallel code for processors equipped with dual-SIMD extensions via vectorizable loop unrolling. The proposed optimization is implemented in both the GNU Compiler Collection (GCC) and the SWGCC710 compilers as an optional compilation pass that can be activated through a single flag. Performance evaluations conducted on Shenwei and Intel processors–using the SPEC CPU 2006, SPEC CPU 2017, and NAS Parallel Benchmarks (NPB)–demonstrate the effectiveness of the proposed method. Compared with the conventional-O3 optimization level, the technique achieves a geometric mean speedup of 1.031 and up to 1.165 for full applications, whereas kernel loops attain 1.168 on the Shenwei platform. Experiments conducted on Intel systems further confirm the optimization’s portability and its consistent performance improvements across diverse architectures.