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<p>Reversible logic is widely used in low-power CMOS design and is the best platform for implementing quantum circuits. Parity-preserving feature in these circuits enhances error detection, which is crucial in quantum computers. Multiplication operation applies in digital signal processing and computer arithmetic, requiring optimal algorithms for efficiency. The Vedic algorithm offers effective techniques for high-speed multiplication operations. This work proposes a 2-bit and two 4-bit parity-preserving reversible multipliers. The first proposed 4-bit circuit is a Vedic multiplier that combines the proposed 2-bit Vedic multiplier with a ripple carry adder; the second 4-bit design employs a partial product circuit and an addition reduction tree. The efficient proposed design in this work achieves average savings of 14% (QC), 27% (CI), and 27% (GO) for the 2-bit design, and 19% (QC), 27% (CI), and 31% (GO) for the 4-bit parity-preserving reversible multipliers compared to the existing designs. The validation of the proposed 2-bit Vedic multiplier design is tested using Quirk online tool, while the proposed 4-bit reversible multipliers are simulated using ModelSim SE 10.6f, both of which confirm the correct functionality of the designs.</p>

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Reversible and fault-tolerant Vedic multiplier with low quantum cost

  • 期刊论文

  • 发表日期：

    2025年11月15日

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  • Shekoofeh Moghimi,
  • Negin Mashayekhi,
  • Mohammad Reza Reshadinezhad

摘要

Reversible logic is widely used in low-power CMOS design and is the best platform for implementing quantum circuits. Parity-preserving feature in these circuits enhances error detection, which is crucial in quantum computers. Multiplication operation applies in digital signal processing and computer arithmetic, requiring optimal algorithms for efficiency. The Vedic algorithm offers effective techniques for high-speed multiplication operations. This work proposes a 2-bit and two 4-bit parity-preserving reversible multipliers. The first proposed 4-bit circuit is a Vedic multiplier that combines the proposed 2-bit Vedic multiplier with a ripple carry adder; the second 4-bit design employs a partial product circuit and an addition reduction tree. The efficient proposed design in this work achieves average savings of 14% (QC), 27% (CI), and 27% (GO) for the 2-bit design, and 19% (QC), 27% (CI), and 31% (GO) for the 4-bit parity-preserving reversible multipliers compared to the existing designs. The validation of the proposed 2-bit Vedic multiplier design is tested using Quirk online tool, while the proposed 4-bit reversible multipliers are simulated using ModelSim SE 10.6f, both of which confirm the correct functionality of the designs.