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<p>The new design paradigms of HPC systems utilizing newly developed CPUs (i.e., ARM and RISC-V) trigger an urgent need for simulators that can handle in an integrated manner both the processing and the network components of a system-under-design (SuD). The presented simulation framework is the first known open-source approach that efficiently integrates well-established simulation subsystems in a single framework with a single notion of time. The framework operates in a fully distributed manner, transparent to the user enabling accurate simulations of both ARM- and RISC-V-based HPC systems interconnected with different networks (e.g., InfiniBand and BXI). Our framework can work in two different modes; in the main one the processing systems and the interconnection networks are simulated at a cycle-accurate manner. The second option can be used if the designer wants to focus on the design space exploration of the architectures/topologies/technologies of the interconnection network, in which case the data collected when running the simulator on the main node, are utilized so as to model and simulate extremely fast different intercommunication infrastructures. The presented framework has been evaluated when simulating widely used benchmarks (HPCG &amp; LAMMPS) on both ARM &amp; RISC-V CPUs; the results demonstrate that our approach has up to 6% performance error in the reported SuD aspects, while the simulation times increase at a very slow pace, when the size of the HPC SuD gets bigger, due to the fully distributed nature of the proposed toolset.</p>

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Distributed fast and accurate simulation platform for advanced ARM- and RISC-V-based HPC systems

  • 期刊论文

  • 发表日期：

    2025年10月21日

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  • Nikolaos Tampouratzis,
  • Ioannis Papaefstathiou,
  • Gabriel Gomez-Lopez,
  • Miguel Sánchez De la Rosa,
  • Jesus Escudero-Sahuquillo,
  • Pedro Javier Garcia

摘要

The new design paradigms of HPC systems utilizing newly developed CPUs (i.e., ARM and RISC-V) trigger an urgent need for simulators that can handle in an integrated manner both the processing and the network components of a system-under-design (SuD). The presented simulation framework is the first known open-source approach that efficiently integrates well-established simulation subsystems in a single framework with a single notion of time. The framework operates in a fully distributed manner, transparent to the user enabling accurate simulations of both ARM- and RISC-V-based HPC systems interconnected with different networks (e.g., InfiniBand and BXI). Our framework can work in two different modes; in the main one the processing systems and the interconnection networks are simulated at a cycle-accurate manner. The second option can be used if the designer wants to focus on the design space exploration of the architectures/topologies/technologies of the interconnection network, in which case the data collected when running the simulator on the main node, are utilized so as to model and simulate extremely fast different intercommunication infrastructures. The presented framework has been evaluated when simulating widely used benchmarks (HPCG & LAMMPS) on both ARM & RISC-V CPUs; the results demonstrate that our approach has up to 6% performance error in the reported SuD aspects, while the simulation times increase at a very slow pace, when the size of the HPC SuD gets bigger, due to the fully distributed nature of the proposed toolset.