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<p>In microelectronics, three-dimensional Network-on-Chip (3D NoC) faces critical challenges in balancing performance and power efficiency due to traffic congestion and routing constraints. To address communication bottlenecks in many-core processors—the foundation of high-performance computing (HPC)—we propose the Congestion-Aware Dynamic Dimension Priority (CA-DDP) routing algorithm. CA-DDP performs three-dimensional collaborative optimization of routing paths, integrating adaptive dimension reconfiguration, non-turning diagonal partitioning, and intelligent load distribution. By applying context-aware, region-specific policies, CA-DDP enhances routing decisions, reduces static power, and improves traffic balance. Experiments show a 10.5% reduction in power and an 8.5% drop in peak latency under varied loads, while ensuring deadlock freedom. As a virtual-channel-free solution, CA-DDP offers a cost-effective paradigm for next-generation 3D NoC, achieving low latency, high throughput, and real-time responsiveness for HPC systems.</p>

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CA-DDP: congestion-aware dynamic dimension prioritization for power-efficient routing algorithm in 3D Network-on-Chip

  • 期刊论文

  • 发表日期：

    2025年10月9日

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  • Jiao Li,
  • Junyu Lu,
  • Feng Ran,
  • Aiying Guo,
  • Xuecheng Sun

摘要

In microelectronics, three-dimensional Network-on-Chip (3D NoC) faces critical challenges in balancing performance and power efficiency due to traffic congestion and routing constraints. To address communication bottlenecks in many-core processors—the foundation of high-performance computing (HPC)—we propose the Congestion-Aware Dynamic Dimension Priority (CA-DDP) routing algorithm. CA-DDP performs three-dimensional collaborative optimization of routing paths, integrating adaptive dimension reconfiguration, non-turning diagonal partitioning, and intelligent load distribution. By applying context-aware, region-specific policies, CA-DDP enhances routing decisions, reduces static power, and improves traffic balance. Experiments show a 10.5% reduction in power and an 8.5% drop in peak latency under varied loads, while ensuring deadlock freedom. As a virtual-channel-free solution, CA-DDP offers a cost-effective paradigm for next-generation 3D NoC, achieving low latency, high throughput, and real-time responsiveness for HPC systems.