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<p>LiDAR-based 3D object detection is crucial for accurate, low-latency perception in autonomous driving. However, the irregular sparsity of point clouds and inefficiencies in traditional architectures pose challenges for real-time deployment on embedded platforms. This paper presents a low-latency FPGA accelerator optimized for sparse neural networks. At the algorithm level, we propose adaptive hybrid sparse convolution (AHSC), which uses a lightweight predictor to dynamically choose between feature pruning, submanifold sparse convolution, or standard convolution, balancing accuracy and sparsity. A two-stage quantization scheme further reduces computation and memory footprint. At the hardware level, we co-design an FPGA accelerator with a fast point cloud preprocessing module, hierarchical pillar memory, and an AHSC-optimized compute array using block-wise fixed-weight dataflows. Implemented on the Xilinx ZCU104, the system achieves 58.36 mAP on KITTI, 34.18 ms latency, 6.287 W power, and 5.053 FPS/W, demonstrating state-of-the-art energy efficiency and validating the effectiveness of the algorithm-hardware co-design.</p>

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Low-latency and energy-efficient FPGA accelerator for sparse neural networks in edge LiDAR-based 3D object detection

  • 期刊论文

  • 发表日期：

    2025年10月8日

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  • Jinyi Li,
  • Yuchen Chen,
  • Xiaofeng Yang,
  • Hengrui Hu,
  • Shengli Lu

摘要

LiDAR-based 3D object detection is crucial for accurate, low-latency perception in autonomous driving. However, the irregular sparsity of point clouds and inefficiencies in traditional architectures pose challenges for real-time deployment on embedded platforms. This paper presents a low-latency FPGA accelerator optimized for sparse neural networks. At the algorithm level, we propose adaptive hybrid sparse convolution (AHSC), which uses a lightweight predictor to dynamically choose between feature pruning, submanifold sparse convolution, or standard convolution, balancing accuracy and sparsity. A two-stage quantization scheme further reduces computation and memory footprint. At the hardware level, we co-design an FPGA accelerator with a fast point cloud preprocessing module, hierarchical pillar memory, and an AHSC-optimized compute array using block-wise fixed-weight dataflows. Implemented on the Xilinx ZCU104, the system achieves 58.36 mAP on KITTI, 34.18 ms latency, 6.287 W power, and 5.053 FPS/W, demonstrating state-of-the-art energy efficiency and validating the effectiveness of the algorithm-hardware co-design.