<p>Logic Locking (LL) is a crucial technique for safeguarding intellectual property (IP) within the semiconductor supply chain. However, the emergence of sophisticated machine learning-based attacks has posed significant challenges to the security of LL designs. This paper introduces TestLock, a novel LL method that leverages circuit testability metrics to enhance resistance against these advanced threats. By strategically selecting node pairs based on their controllability and observability, TestLock significantly obfuscates the circuit’s internal structure, making it considerably more difficult for attackers to identify and exploit vulnerabilities. The proposed method is lightweight in computation, while introducing only modest hardware overhead, making it applicable to a wide range of hardware designs. Furthermore, due to the systematic nature of SCOAP-guided node selection and the scalability of the approach, TestLock can be effectively integrated into large-scale systems. As modern security-critical applications increasingly rely on high-throughput and real-time performance, TestLock offers a logic-level defense mechanism that aligns with the requirements of secure implementations. Additionally, evaluation against state-of-the-art attacks, including MuxLink and SCOPE, demonstrates that TestLock’s superior performance in preserving IP integrity. Our results indicate a substantial reduction in attack accuracy, with a 57.13% decrease observed for MuxLink and a 24.22% reduction for SCOPE. TestLock offers a robust and effective defense against these attacks, safeguarding IP from unauthorized access and reverse engineering.</p>