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<p>Convolutional neural networks (CNNs) are typically implemented using GPUs, but their power consumption and area efficiency become critical challenges as data complexity scales. In this work, we propose a fully parallel CNN (FP-CNN) architecture that employs single-memristor crossbar arrays per weight, unlike conventional designs requiring paired arrays, enabling the computation of multiple feature maps in one processing cycle. To optimize area and power, our design utilizes only three CNN layers and an absolute activation function to enhance feature extraction. We incorporate memristor synaptic modeling with noise and error injection to closely emulate realistic hardware behavior. Simulation results on the MNIST handwritten digit classification task demonstrate notable improvements over prior works, achieving up to 39.41% reduction in power consumption and 17.48% reduction in chip area, while maintaining a high CNN classification accuracy of 98.63% despite using a minimalist three-layer architecture. Moreover, using 128-level memristors, the network maintains 98.28% accuracy under chip simulation conditions, showcasing robustness to device-level non-idealities.</p>

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Efficient fully parallel convolutional neural network architecture using 1-memristor and 1-transistor (1M1T)

  • 期刊论文

  • 发表日期：

    2025年8月26日

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  • Ahmadreza Yosefzadeh Chari,
  • Morteza Gholipour,
  • Mohammadreza Hassanzadeh

摘要

Convolutional neural networks (CNNs) are typically implemented using GPUs, but their power consumption and area efficiency become critical challenges as data complexity scales. In this work, we propose a fully parallel CNN (FP-CNN) architecture that employs single-memristor crossbar arrays per weight, unlike conventional designs requiring paired arrays, enabling the computation of multiple feature maps in one processing cycle. To optimize area and power, our design utilizes only three CNN layers and an absolute activation function to enhance feature extraction. We incorporate memristor synaptic modeling with noise and error injection to closely emulate realistic hardware behavior. Simulation results on the MNIST handwritten digit classification task demonstrate notable improvements over prior works, achieving up to 39.41% reduction in power consumption and 17.48% reduction in chip area, while maintaining a high CNN classification accuracy of 98.63% despite using a minimalist three-layer architecture. Moreover, using 128-level memristors, the network maintains 98.28% accuracy under chip simulation conditions, showcasing robustness to device-level non-idealities.