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<p>Optimizing network-on-chip (NoC) architectures is critical for balancing reliability and performance. This study simultaneously optimizes mesh-based NoC architectures with 5-port routers and XY routing algorithm and aims to improve reliability and reduce average packet latency using varying constraints on buffer size. Buffer size, which plays a pivotal role in affecting average packet latency, cost, and reliability, served as a central optimization variable. The Non-dominated Sorting Genetic Algorithm II was exploited to obtain a Pareto front (the set of optimal trade-off solutions) between multiple objectives. Performance validation using the Garnet 2.0 simulator confirmed the approach’s accuracy. Extensive simulations are provided with detailed insights across NoC dimensions ranging from <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7733_Article_IEq1.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="39" /> </InlineMediaObject> <EquationSource Format="TEX">\(3\times 3\)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>3</mn> <mo>×</mo> <mn>3</mn> </mrow> </math></EquationSource> </InlineEquation> to <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7733_Article_IEq2.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="39" /> </InlineMediaObject> <EquationSource Format="TEX">\(8\times 8\)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>8</mn> <mo>×</mo> <mn>8</mn> </mrow> </math></EquationSource> </InlineEquation> networks for both synthetic traffic (uniform and hotspot) and real traffic. For instance, in a <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="11227_2025_7733_Article_IEq3.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="39" /> </InlineMediaObject> <EquationSource Format="TEX">\(4\times 4\)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>4</mn> <mo>×</mo> <mn>4</mn> </mrow> </math></EquationSource> </InlineEquation> mesh network with 22 Pareto front points under uniform traffic, we achieved the lowest average packet latency of 18.0001 cycles and a minimal Failures in Time rate of 4213 failures per billion hours.</p>

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Simultaneous optimization of network-on-chip to improve reliability and reduce average packet latency considering buffer size constraints

  • 期刊论文

  • 发表日期：

    2025年8月21日

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  • Hesam Abdolhosseini,
  • Hamid R. Zarandi,
  • Arman Gheysari

摘要

Optimizing network-on-chip (NoC) architectures is critical for balancing reliability and performance. This study simultaneously optimizes mesh-based NoC architectures with 5-port routers and XY routing algorithm and aims to improve reliability and reduce average packet latency using varying constraints on buffer size. Buffer size, which plays a pivotal role in affecting average packet latency, cost, and reliability, served as a central optimization variable. The Non-dominated Sorting Genetic Algorithm II was exploited to obtain a Pareto front (the set of optimal trade-off solutions) between multiple objectives. Performance validation using the Garnet 2.0 simulator confirmed the approach’s accuracy. Extensive simulations are provided with detailed insights across NoC dimensions ranging from \(3\times 3\) 3 × 3 to \(8\times 8\) 8 × 8 networks for both synthetic traffic (uniform and hotspot) and real traffic. For instance, in a \(4\times 4\) 4 × 4 mesh network with 22 Pareto front points under uniform traffic, we achieved the lowest average packet latency of 18.0001 cycles and a minimal Failures in Time rate of 4213 failures per billion hours.