Scholarlink

<p>With the further reduction in transistor size, the probability of component failures in Network-on-Chip increases significantly, and routers, as the main components of NoC, may lead to network communication interruption in case of failure. Most existing fault-tolerant schemes are designed based on rerouting strategies, which can create network hotspots, while increasing the number of faulty routers may lead to packet loss. Previous fault-tolerant schemes based on bypass routing can alleviate these problems, but bypass routing is restricted to faulty routers and is susceptible to network traffic distribution, resulting in high packet delays. In this paper, we propose a fault-tolerant router architecture based on dynamic bypass, where the use of bypasses is no longer restricted to faulty routers. For a healthy router, packets that pass through the bypass channel do not interfere with normal internal channel transmission, which improves packet transmission efficiency. Based on this architecture, we propose two dynamic bypass fault-tolerant schemes, FABDB and FABDB++, and FABDB++ offers more flexible bypass usage conditions compared to FABDB. The experimental results show that our proposed fault-tolerant scheme reduces the delay by 36.2% and improves the throughput by 24.3% on average compared with the existing schemes. The reliability is above 99% in the presence of 8 faulty routers in an 8x8 mesh. The proposed scheme achieves low dynamic power overhead and hardware resource overhead while maintaining high reliability.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Fabdb: a low-latency fault-tolerant architecture based on dynamic bypass for network-on-chip

  • 期刊论文

  • 发表日期：

    2025年6月13日

查看全文
  • Yiming Ouyang,
  • Zhuoxuan Ji,
  • Jianhua Li,
  • Huaguo Liang

摘要

With the further reduction in transistor size, the probability of component failures in Network-on-Chip increases significantly, and routers, as the main components of NoC, may lead to network communication interruption in case of failure. Most existing fault-tolerant schemes are designed based on rerouting strategies, which can create network hotspots, while increasing the number of faulty routers may lead to packet loss. Previous fault-tolerant schemes based on bypass routing can alleviate these problems, but bypass routing is restricted to faulty routers and is susceptible to network traffic distribution, resulting in high packet delays. In this paper, we propose a fault-tolerant router architecture based on dynamic bypass, where the use of bypasses is no longer restricted to faulty routers. For a healthy router, packets that pass through the bypass channel do not interfere with normal internal channel transmission, which improves packet transmission efficiency. Based on this architecture, we propose two dynamic bypass fault-tolerant schemes, FABDB and FABDB++, and FABDB++ offers more flexible bypass usage conditions compared to FABDB. The experimental results show that our proposed fault-tolerant scheme reduces the delay by 36.2% and improves the throughput by 24.3% on average compared with the existing schemes. The reliability is above 99% in the presence of 8 faulty routers in an 8x8 mesh. The proposed scheme achieves low dynamic power overhead and hardware resource overhead while maintaining high reliability.