Efficient VLSI implementations of singular value decomposition
摘要
Singular value decomposition (SVD) plays a major role in data science for the reduction of the dimensions. Two most widely used techniques in the hardware implementation of the SVD are Jacobi (or two sided) SVD and Hestenes-Jacobi (or one sided) SVD. In this article, efficient very large scale integration implementations Jacobi SVD are proposed. In the first proposed implementation, the entire SVD architecture is segregated into control and data paths. The control path co-ordinates the heavy intensive arithmetic operations that are required to be performed for the calculation of SVD in data path. This proposed design is implemented in 45 nm CMOS technology with Cadence. In the second proposed implementation, the Cortex-A0 core co-ordinates the arithmetic operations for the SVD in the co-processor using Zynq 7000 FPGA platform. In the third proposed implementation, partial reconfiguration based co-processor unit is co-ordinated by the Cortex-A0 core to perform the required operations of the SVD. In all the three proposed implementations, the hardware resources are reduced as compared with the various existing designs. In other words, the synthesis results prove that the proposed designs achieve significant reduction in area and power as compared with the existing designs. For example, the proposed ASIC based