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<p>Convolutional Neural Networks (CNNs) proved highly successful in various applications, including image classification. CNNs demand a massive number of mathematical operations that represent a challenge in hardware implementation, especially for limited-resource devices or edge-computing devices. This paper presents Binary Weight CNN (BW-CNN) accelerator that can be deployed on Field Programmable Gate Array (FPGA). The BW-CNN provides efficient hardware optimization, by using 1-bit representation for weights and 2-bit representation for activations to minimize the model size and reduce the number of required multiplications. Moreover, binary weights enable the system to avoid memory access time bottleneck for reading the weights because they are saved on-chip. The BW-CNN supports hardware/software co-design approach for hardware acceleration. The proposed BW-CNN is implemented using Virtex UltraScale FPGA VCU108 Evaluation Kit. The BW-CNN is evaluated on the Modified National Institute of Standards and Technology (MNIST) dataset achieving 98.45% accuracy and consumes power of 3.599 W.</p>

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HW-SW co-design of image classification accelerator on FPGA

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2025年5月31日

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  • Ratshih Sayed,
  • H. H. Draz,
  • Haytham Azmi

摘要

Convolutional Neural Networks (CNNs) proved highly successful in various applications, including image classification. CNNs demand a massive number of mathematical operations that represent a challenge in hardware implementation, especially for limited-resource devices or edge-computing devices. This paper presents Binary Weight CNN (BW-CNN) accelerator that can be deployed on Field Programmable Gate Array (FPGA). The BW-CNN provides efficient hardware optimization, by using 1-bit representation for weights and 2-bit representation for activations to minimize the model size and reduce the number of required multiplications. Moreover, binary weights enable the system to avoid memory access time bottleneck for reading the weights because they are saved on-chip. The BW-CNN supports hardware/software co-design approach for hardware acceleration. The proposed BW-CNN is implemented using Virtex UltraScale FPGA VCU108 Evaluation Kit. The BW-CNN is evaluated on the Modified National Institute of Standards and Technology (MNIST) dataset achieving 98.45% accuracy and consumes power of 3.599 W.