Scholarlink

<p>Traditional instruction selection methods fail to fully exploit the very long instruction word (VLIW) architecture’s efficient scalar instructions. We propose an optimized instruction selection method based on classification node merging. This method abstracts scalar intermediate instructions into nodes and divides them into associated and similar ones according to operational semantics. Combined with the VLIW architecture’s instruction set features and guided by the instruction cost model, the nodes are merged and optimized to select efficient instructions. We design an instruction generation framework that swiftly converts the low level virtual machine intermediate representation into the instruction sequence of the target architecture. The experimental results show that, compared with the instruction sequence generated by M7002-cc, the instruction sequence generated with the solution proposed in this paper exhibits an average execution performance that is up to 54% higher on the FT-M7002 hardware platform.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Instruction selection optimization for VLIW architecture based on classification node merging

  • 期刊论文

  • 发表日期：

    2025年5月2日

查看全文
  • Fangjun Liu,
  • Huifu Zhang,
  • Yonghua Hu,
  • Anxing Xie,
  • Wei Cao,
  • Shangfeng Mo

摘要

Traditional instruction selection methods fail to fully exploit the very long instruction word (VLIW) architecture’s efficient scalar instructions. We propose an optimized instruction selection method based on classification node merging. This method abstracts scalar intermediate instructions into nodes and divides them into associated and similar ones according to operational semantics. Combined with the VLIW architecture’s instruction set features and guided by the instruction cost model, the nodes are merged and optimized to select efficient instructions. We design an instruction generation framework that swiftly converts the low level virtual machine intermediate representation into the instruction sequence of the target architecture. The experimental results show that, compared with the instruction sequence generated by M7002-cc, the instruction sequence generated with the solution proposed in this paper exhibits an average execution performance that is up to 54% higher on the FT-M7002 hardware platform.