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<p>As multicore processors become the standard for performance scaling, challenges related to predictability and repeatability arise, particularly in real-time and cyber-physical systems. Precision-Timed (PRET) architectures address this by enforcing deterministic execution, but current designs primarily exploit thread-level parallelism (TLP) while underutilizing instruction-level parallelism (ILP). This limitation can lead to suboptimal performance in workloads with limited TLP. To address this, we propose AccPRET, a novel quad-core architecture that integrates a coarse-grained reconfigurable array (CGRA) with a PRET processor, enabling the simultaneous exploitation of TLP and ILP while maintaining real-time guarantees. Our FPGA-based evaluation demonstrates that AccPRET achieves speedups of up to 6.69 × over VLIW architectures and 6.33 × over out-of-order architectures, with a 36.76 × improvement in multicore execution over single-threaded execution. Furthermore, AccPRET delivers these performance gains while consuming 4% less area than an out-of-order processor and only 2.2x the area of a VLIW processor. These results highlight the viability of integrating reconfigurable computing into deterministic architectures, offering a promising approach to bridging high performance and predictable execution. Future research will explore energy-efficient scheduling, hybrid memory hierarchies, scalable interconnects, and compiler/toolchain support to further enhance AccPRET’s capabilities in real-time and embedded computing domains.</p>

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AccPRET: a proposal of a multicore architecture with reconfigurable accelerators and time predictability

  • 期刊论文

  • 发表日期：

    2025年3月13日

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  • Hadley Siqueira,
  • Marcio Kreutz

摘要

As multicore processors become the standard for performance scaling, challenges related to predictability and repeatability arise, particularly in real-time and cyber-physical systems. Precision-Timed (PRET) architectures address this by enforcing deterministic execution, but current designs primarily exploit thread-level parallelism (TLP) while underutilizing instruction-level parallelism (ILP). This limitation can lead to suboptimal performance in workloads with limited TLP. To address this, we propose AccPRET, a novel quad-core architecture that integrates a coarse-grained reconfigurable array (CGRA) with a PRET processor, enabling the simultaneous exploitation of TLP and ILP while maintaining real-time guarantees. Our FPGA-based evaluation demonstrates that AccPRET achieves speedups of up to 6.69 × over VLIW architectures and 6.33 × over out-of-order architectures, with a 36.76 × improvement in multicore execution over single-threaded execution. Furthermore, AccPRET delivers these performance gains while consuming 4% less area than an out-of-order processor and only 2.2x the area of a VLIW processor. These results highlight the viability of integrating reconfigurable computing into deterministic architectures, offering a promising approach to bridging high performance and predictable execution. Future research will explore energy-efficient scheduling, hybrid memory hierarchies, scalable interconnects, and compiler/toolchain support to further enhance AccPRET’s capabilities in real-time and embedded computing domains.