Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications

In the pursuit of high-performance designs for error-resilient applications, approximate computing emerges as a key strategy. This paper introduces an innovative approximate multiplier, leveraging two highly efficient compressors. These compressors operate in tandem across two stages, strategically compensating for errors and culminating in a multiplier that maintains accuracy and significantly reduces delay in the final stage. The proposed method is specifically tailored for applications reliant on multiplication, such as image processing and neural networks. HSPICE simulations were conducted using 7 nm FinFET technology to gauge its efficacy. Results indicate a remarkable 82% reduction in power-delay product (PDP) compared to traditional multipliers. Moreover, system-level simulations underscore the practicality of the proposed multiplier in real-world applications like image processing and artificial intelligence, revealing minimal compromise in accuracy. This work contributes a nuanced perspective to approximate computing, presenting a multiplier poised to elevate efficiency without sacrificing precision in critical domains.