Optimizing computer vision algorithms with TVM on VLIW architecture based on RVV

In recent years, many computer vision tasks, including object detection, recognition, and segmentation, have been accomplished using deep learning models. However, certain computer vision algorithms, such as affine transformation, image blur, edge detection, and histogram equalization, remain irreplaceable in deep learning models. To accelerate the execution times of these computer vision algorithms, in this paper, these algorithms are implemented and optimized on the Tensor Virtual Machine (TVM) and a very long instruction word (VLIW) architecture based on the RISC-V instruction set. The TVM is a deep learning compiler framework on which deep learning tasks can be optimized across various hardware platforms through multiple levels of optimization. In the VLIW architecture, groups of instructions are concurrently executed, thereby leveraging instruction-level parallelism to improve performance. Computer vision applications, which are largely composed of fixed operations, are frequently optimized by deploying these applications on digital signal processors (DSPs) with VLIW architectures. Thus, we propose a 6-way VLIW architecture composed of two integer units, two floating-point or double-precision units, and two vector units on the basis of the RISC-V vector extension(RVV) for VLIW architectures. In our research, we use TVM tensor expressions to implement computer vision algorithms and optimize performance via the MetaSchedule for the proposed VLIW RVV architecture. In our experiments using the Gem5 simulator, the proposed VLIW architecture demonstrated significant performance improvements, achieving up to 26.08 times faster execution in histogram equalization than the RV64 baseline. We evaluated the performance of four computer vision algorithms across various CPU architectures and memory configurations, highlighting the effectiveness of combining traditional algorithms with machine learning compiler frameworks and specialized hardware to increase computational efficiency.