Minimum linear arrangement and embedding of (K11 − C11)n into specific graphs with optimal wirelength calculation
摘要
Interconnection networks, composed of numerous integrated circuits (ICs), form complex structures crucial to many parallel computing systems. The effectiveness of very large scale integration (VLSI) relies on various parameters that influence the design’s cost. In this article, one such crucial parameter, called wirelength, has been studied. Graph embedding is a tool used in the design of VLSI layouts. A graph’s optimal linear layout, also known as minimum linear arrangement (MinLA), is achieved by embedding its vertices onto a line topology. The network topology of