Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

On-chip networks (NoCs) have become a popular choice for designing large multiprocessor architectures. Software-based emulation is often used to perform the design verification. However, if the considered design is sufficiently large, software-based emulation becomes impractically slow. To avoid this limitation, multi-FPGA emulation was introduced, where multiple interconnected FPGAs collectively emulate a single circuit. The number of external FPGA pins is often insufficient for emulating large network-on-chip designs accurately. As a result, the overall emulation frequency has to be severely limited. We propose a method for accelerating multi-FPGA emulation by reducing the amount of data FPGAs need to transmit to each other. To achieve cycle-accurate emulation in the absence of constant transmission latency, synchronous messaging is implemented. The proposed method was tested on a functioning prototype. It is shown that the use of our method for multi-FPGA emulation of large NoC designs can reach several orders.