Iterative construction of energy and quality-efficient approximate multipliers utilizing lower bit-length counterparts

With the increasing complexity of digital systems, managing power dissipation and energy consumption in digital circuits, particularly in emerging embedded systems for artificial intelligence and signal processing applications, has become a challenging issue. The emerging paradigm of approximate computing offers the potential to reduce energy consumption and enhance speed by trading accuracy. This paper introduces several 4-bit approximate multipliers and outlines a systematic approach for constructing extended bit-length multipliers by leveraging lower bit-length counterparts. Our evaluations confirm that, in comparison with state-of-the-art approximate multipliers, the proposed multipliers demonstrate energy reduction of up to 50, 76, and 83% in 8-bit, 16-bit, and 32-bit multipliers, respectively. Additionally, the reduction in energy-delay product (EDP) reaches up to 86, 93, and 97%, correspondingly. The efficiency of the proposed approximate multipliers has been explored and confirmed in executing various image processing algorithms, a regression model developed for stock price prediction, and in executing quadrature amplitude demodulation.