ITER: an ITERative approach for inter-core timing analysis in statically scheduled cyclic executive systems on COTS multicore platforms for CRTES

Off-the-shelf multicore systems are increasingly used in real-time fields, but hardware resource contention remains a key challenge. This work focuses on statically scheduled systems, common in real-time computing, and introduces a novel model for calculating worst-case contention delays. Under realistic assumptions, our model provides tight upper limits on these delays, considering the timing interference from other cores and their task sets. We present comprehensive evaluations demonstrating that our approach yields more accurate contention bounds compared to existing solutions. Additionally, we introduce an automated framework that simplifies the integration of our model into real-world scenarios, making it practical for industry professionals. This work not only tackles a critical issue in real-time multicore systems but also offers a precise, practical solution for managing inter-core timing interference.