A fast and energy-efficient hybrid 4–2 compressor for multiplication in nanotechnology

In this paper, a novel high-speed and energy-efficient 4–2 compressor cell is proposed using carbon nanotube field-effect transistors. The proposed compressor is realized efficiently based on NAND–NOR gates and multiplexers. To estimate the performance of the presented design, simulations are carried out using Synopsis HSPICE under different conditions. The results demonstrate the improvement of the proposed design compared to the best reference designs in terms of delay and energy consumption, by 20–26%, respectively. Also, the susceptibility of the proposed design against the process, voltage, temperature (PVT), and noise variations is examined. It is robust against PVT variations and high amplitude of noises compared with its counterpart. Further, embedding the proposed compressor in an 8 × 8-bit binary multiplier demonstrates that it has better speed and energy consumption with regard to its counterparts.