Practical circuit optimization algorithm for quantum simulation based on template matching

We propose a circuit optimization algorithm that facilitates the implementation of various applications on noise intermediate-scale quantum (NISQ) devices. The algorithm is hardware-independent and reduces the overall circuit cost of Hamiltonian simulation, particularly by minimizing the number of CNOT gates. Our approach employs a sub-circuit synthesis scheme for intermediate representation and proposes the practical template matching algorithm (TM) for gate elimination to minimize CNOT counts. This algorithm demonstrates low complexity and enhances the circuit performance of Hamiltonian simulations. In our simulations, we benchmarked different algorithms across various Hamiltonian models to quantify and compare the benefits of our approach. Compared with advanced generic compilers and specific quantum compilers, the results obtained from simulating our algorithm show an average reduction of 1.5 \(\times \) $\times$ (up to 2.56 \(\times \) $\times$ ) in CNOT counts, and 1.4 \(\times \) $\times$ (up to 3.1 \(\times \) $\times$ ) in circuit depth. This improvement further advances the practical application of Hamiltonian simulation in the NISQ era.