Ultra low power reversible arithmetic processor based on QCA

Quantum dot Cellular Automata (QCA) may be viewed as the poten- tial digital logic design alternative to supplant the current CMOS Technol- ogy. The logical design is based on the polarization of electrons to transfer information which results in a huge improved performance metric in terms of speed, power & area. This paper demonstrates a Reversible Arithmetic Processor (RAP) architecture design with Reversible Multiplexer (RM) and Reversible Functional Gate in QCA. The QCA Designer-E simulation tool has been used to design and verify all the proposed archi- tecture and the energy dissipation has been simulated using a coherent vector energy engine setup. The total and average energy dissipation per cycle of our proposed RAP using QCA are 3.91 × 10⁻¹ eV and 3.56 × 10⁻² eV respectively. Moreover, the power dissipation of proposed RAP is 1.3 nW. Regarding cell count, area, latency, and energy dissipation, the proposed architecture beats out the existing architecture.