Design method for unbalanced ternary logic family based on binary memristors

This paper proposes a design method for unbalanced ternary logic family based on hybrid design of binary memristors and CMOS transistors, building on the foundational positive ternary logic circuits. By using the symmetry of negative and positive ternary logics, negative ternary TAND, TOR, TI, 1-3 decoder and 2-9 decoder are derived from the previously designed positive ternary basic logic gate circuits. Furthermore, negative ternary XOR, XNOR, 3-1 encoder and 9-2 encoder are design-improved. For the first time, unbalanced ternary priority encoders are proposed, including a 3-1 priority encoder and a 9-2 priority encoder, of which the former is implemented with only seven memristors. The functionalities of these circuits are demonstrated through LTSpice simulations. Finally, hardware experiments were performed on a stable 20 \(\times \) $\times$ 20 ZnO-based resistive switch array. Subsequent design of more complex digital logic circuits can benefit from this work.