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<p>The exponential growth of the number of devices connected to the Internet and the use of IoT applications increases the amount of data exchange over public channels in low-cost and low-power embedded systems. Images are the most widely shared files, and standard symmetric algorithms such as the Advanced Encryption Standard (AES) are optimized for text but not image encryption. Consequently, new approaches like chaotic encryption have attracted researchers’ interest. Chaotic encryption schemes have been analyzed mostly from a software standpoint, but recent advancements in the field, through the use of discrete chaotic maps, enabled the development of simpler hardware implementations of ciphers with promising reductions in power and cost and increased performance. This work presents the Field-Programmable Gate Array (FPGA) implementation of a simultaneous permutation-diffusion chaotic encryption scheme utilizing a discrete-space chaotic map. The FPGA implementation of the cipher is analyzed considering area, maximum frequency, and power consumption, and comparisons are made with the AES. The proposed algorithm has a satisfactory trade-off between area, power and performance, obtaining a peak throughput 59% higher than state-of-the-art symmetric ciphers in the literature. Thus, the proposed cipher shows that chaotic ciphers are viable for both high-performance and low-power embedded devices. Tests verified the security of the proposed cipher against statistical, differential, brute-force, and chosen plain-text attacks.</p>

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FPGA implementation of low cost and low power chaotic encryption scheme based on a discrete-space chaotic map

  • 期刊论文

  • 发表日期：

    2025年1月4日

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  • João Inácio Moreira Bezerra,
  • Gustavo Machado,
  • Rafael Iankowski Soares,
  • Vinícius Valduga de Almeida Camargo,
  • Alexandre Molter

摘要

The exponential growth of the number of devices connected to the Internet and the use of IoT applications increases the amount of data exchange over public channels in low-cost and low-power embedded systems. Images are the most widely shared files, and standard symmetric algorithms such as the Advanced Encryption Standard (AES) are optimized for text but not image encryption. Consequently, new approaches like chaotic encryption have attracted researchers’ interest. Chaotic encryption schemes have been analyzed mostly from a software standpoint, but recent advancements in the field, through the use of discrete chaotic maps, enabled the development of simpler hardware implementations of ciphers with promising reductions in power and cost and increased performance. This work presents the Field-Programmable Gate Array (FPGA) implementation of a simultaneous permutation-diffusion chaotic encryption scheme utilizing a discrete-space chaotic map. The FPGA implementation of the cipher is analyzed considering area, maximum frequency, and power consumption, and comparisons are made with the AES. The proposed algorithm has a satisfactory trade-off between area, power and performance, obtaining a peak throughput 59% higher than state-of-the-art symmetric ciphers in the literature. Thus, the proposed cipher shows that chaotic ciphers are viable for both high-performance and low-power embedded devices. Tests verified the security of the proposed cipher against statistical, differential, brute-force, and chosen plain-text attacks.