Implementation of a novel adaptive coding using VLSI architecture for data compression in image processing

Image Compression is one of the emerging techniques of a Digital System for storing and retrieving of digital information. The main challenge in implementing Image Compression is to maintain the accuracy of the retrieved data. As the encoding techniques used for data compression are computationally intensive, new hardware architectures are required so that the processing of image consumes less space with increase in computation speed, reduction in area and power consumption. In this paper we address this problem and developed a Dynamic Adaptive coding technique based on probability of occurrence,where the variable and fixed length code are fused to generate a code word for eliminating the extra bit encountered at the entropy coder. Here the Entropy code has a maximum search overhead of 6 match per 4-bit pattern. Wherein a maximum of 5-bit search is observed in proposed approach. This reduces a search overhead of (N⨉m)-1 iterations. Here N is the number of unique patterns and m is the block size. The proposed architecture is developed using Very high speed integrated circuit Hardware Descriptive Language (VHDL) and implemented using Xilinx Aldec’s Field Programmable Gate Array (FPGA). The adaptive coding approach attains a compression of 35% more as compared to the entropy coding. The implementation on to a targeted Xilinx FPGA results in power minimization and area coverage reduction. The speed of operation is observed to be improved by 135 MHz. The validation of proposed approach is made on image data to observe the coding accuracy. The mean square error of the output image is reduced by 35% with an increase in the signal to noise ratio of the output image.