RETRACTED ARTICLE: Modeling and simulation of FIR filter using distributed arithmetic algorithm on FPGA

In many industries and telecommunication system there is a need for digital signal processing for fast transfer of data between two points or devices with low power consumption and considerable hardware resources (circuit size and speed). Finite Impulse Response (FIR) filters play an important role in many signal processing applications and telecommunication systems. This paper propose the design and implementation of 4-bit FIR Filter using Distributed Arithmetic (DA) Algorithms, which substitute, multiply and accumulate operation with series of Look Up Table (LUT). The proposed FIR filter is implemented in high-density field programmable logic devices (FPGAs) and designed using very high-speed integrated circuit hardware description language (VHDL) and verified using Xilinx ISE 14.7 tool and simulator. The proposed, modified and optimized DA provided the multiplication and accumulation free calculation of inner product data of FIR filter and this consecutively reduces the size and power dissipation of circuit. DA is one of the methods to implement FIR filters that impact the storage resource and the calculating speed, which make the memory size smaller and the operation speed faster. The simulated proposed structure required nearly 40% less cells, 35% less LUT pairs and 4% less power consumption with existing structure.