<p>In photonic quantum computing and quantum information processing, photon number resolution is crucial for generating highly non-classical quantum states. Superconducting transition-edge sensors (TESs) are considered one of the most effective photon number-resolving detectors for this purpose. However, the current timing properties of TESs, such as timing jitter (a few ns) and recovery time (several hundred ns), are insufficient, limiting the operational speed of quantum applications. To address the potential for improving TES timing performance, we have proposed an improved calculation to derive TES timing jitter. Our calculations including the effect of the SQUID noise indicate that expanding the electrical bandwidth of the external voltage amplifier and optimizing the inductance to match that bandwidth, can significantly improve timing jitter. According to our model, timing jitter 1 ns FWHM is achievable with an input inductance of 0.35 nH and an electrical bandwidth of 1 GHz. Additionally, we have shown that with our TES and SQUID parameters, the lowest achievable timing jitter is approximately 0.71&#xa0;ns FWHM. Achieving an even lower jitter would require a redesign aimed at further reducing the SQUID noise.</p>

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Calculation and Proposal for Improving the Timing Jitter of Transition-Edge Sensors

  • Akihiro Kato,
  • Kaori Hattori,
  • Sachiko Takasu,
  • Joern Beyer,
  • Daiji Fukuda

摘要

In photonic quantum computing and quantum information processing, photon number resolution is crucial for generating highly non-classical quantum states. Superconducting transition-edge sensors (TESs) are considered one of the most effective photon number-resolving detectors for this purpose. However, the current timing properties of TESs, such as timing jitter (a few ns) and recovery time (several hundred ns), are insufficient, limiting the operational speed of quantum applications. To address the potential for improving TES timing performance, we have proposed an improved calculation to derive TES timing jitter. Our calculations including the effect of the SQUID noise indicate that expanding the electrical bandwidth of the external voltage amplifier and optimizing the inductance to match that bandwidth, can significantly improve timing jitter. According to our model, timing jitter 1 ns FWHM is achievable with an input inductance of 0.35 nH and an electrical bandwidth of 1 GHz. Additionally, we have shown that with our TES and SQUID parameters, the lowest achievable timing jitter is approximately 0.71 ns FWHM. Achieving an even lower jitter would require a redesign aimed at further reducing the SQUID noise.