Design and First Tests From Room Temperature to 200 mK of a 16-to-1 CMOS Multiplexing ASIC for High Impedance NbSi TESs

Achieving high spectral and spatial resolution of wide astrophysical objects in the X-ray band will be the main focus of the future X-ray space telescopes. We explore a new technological solution based on high impedance NbSi TES detectors ( \(\sim \) $\sim$ 2 M \(\Omega \) $\mathrm{\Omega }$ ) enabling the transfer of the pre-amplification stage to higher temperatures (4 K) and the use of a 50 mK CMOS time-division multiplexer to reduce power dissipation at 50 mK. We present the design and first tests, down to 200 mK, of this CMOS ASIC eventually able to work down to 50 mK and multiplexing 16 high impedance NbSi TES detectors to one 4 K amplifier with a total power budget under 2  \(\mu \) $\mu$ W. In parallel of this development we fabricated 4-by-4 NbSi pixel matrices to build a complete demonstrator (comprising the detector array, presented in another paper to be published, the multiplexing ASIC and the 4 K amplification stage). We aim at a multiplexing frame time of 48  \(\mu \) $\mu$ s leaving 3  \(\mu \) $\mu$ s for reading-out each high impedance pixel. The multiplexing ASIC embeds parasitic capacity compensation techniques.