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<p>Effective electrical isolation between adjacent MOS transistors is critical for integrated circuits, and the profile control of shallow trench isolation (STI) top corner rounding (TCR) directly affects device performance and reliability. This work presents two in‑situ plasma‑etching schemes for STI TCR suitable for high‑volume manufacturing at the 150&#xa0;nm node. Scheme I, an etch‑dominated approach, achieves precise shoulder width control through oxide over‑etch time, with 2.5&#xa0;s identified as the optimal condition (process capability Ca = 0.005, Cp = 1.65, Cpk = 1.64). Scheme II, a deposition‑dominated approach, forms the shoulder via a plasma polymer step and exhibits a reversed dense/isolated loading effect. Defect mechanism analysis reveals that masking defects originate from polymer collapse under ion bombardment, while nodule defects arise from chamber particles or by‑products. Masking defects are eliminated by reducing the CH<sub>2</sub>F<sub>2</sub> ratio, and nodule defects are reduced by 76.7% via Si:Si<sub>3</sub>N<sub>4</sub> selectivity optimization (from 57:1 to 6:1), with total yield loss below 0.2%. Wafer acceptance test (WAT) results confirm that the optimized shoulder suppresses the inverse narrow width effect and reduces leakage while maintaining gate oxide integrity. For the first time, this work provides a systematic comparison of two plasma TCR schemes, quantitative defect analysis, and multi‑product process capability validation, establishing a robust manufacturing solution for STI TCR.</p>

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Enhancement of shallow trench isolation top corner rounding for high-volume manufacturing

  • 期刊论文

  • 发表日期：

    2026年7月1日

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  • Ran Wang,
  • You-Cheng Lin,
  • Zi-Ren Lin,
  • Dong-Yi Lin,
  • Zhi-Qiang Yang,
  • Xin-Yao Yu

摘要

Effective electrical isolation between adjacent MOS transistors is critical for integrated circuits, and the profile control of shallow trench isolation (STI) top corner rounding (TCR) directly affects device performance and reliability. This work presents two in‑situ plasma‑etching schemes for STI TCR suitable for high‑volume manufacturing at the 150 nm node. Scheme I, an etch‑dominated approach, achieves precise shoulder width control through oxide over‑etch time, with 2.5 s identified as the optimal condition (process capability Ca = 0.005, Cp = 1.65, Cpk = 1.64). Scheme II, a deposition‑dominated approach, forms the shoulder via a plasma polymer step and exhibits a reversed dense/isolated loading effect. Defect mechanism analysis reveals that masking defects originate from polymer collapse under ion bombardment, while nodule defects arise from chamber particles or by‑products. Masking defects are eliminated by reducing the CH2F2 ratio, and nodule defects are reduced by 76.7% via Si:Si3N4 selectivity optimization (from 57:1 to 6:1), with total yield loss below 0.2%. Wafer acceptance test (WAT) results confirm that the optimized shoulder suppresses the inverse narrow width effect and reduces leakage while maintaining gate oxide integrity. For the first time, this work provides a systematic comparison of two plasma TCR schemes, quantitative defect analysis, and multi‑product process capability validation, establishing a robust manufacturing solution for STI TCR.