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<p>In this work, a systematic investigation is conducted on the electrical characteristics and interface engineering of metal–oxide–semiconductor (MOS) capacitors employing a novel Sc<sub>2</sub>O<sub>3</sub>/SiO₂ gate dielectric stack. Emphasis is placed on elucidating the critical roles of post-deposition annealing processes and the interfacial SiO₂ layer in modulating the interfacial quality and overall device performance. Detailed capacitance–voltage (C–V) and conductance–voltage (G–V) analyses demonstrated a marked improvement in critical electrical parameters, most notably a significant reduction in effective oxide charge (N<sub>eff</sub> ≈ 2.5 × 10<sup>1</sup>⁰ cm⁻<sup>2</sup>) and interface trap density (D<sub>it</sub> ≈ 5.3 × 10<sup>1</sup>⁰ cm⁻<sup>2</sup>) following annealing at 600&#xa0;°C, underscoring effective defect passivation. Barrier height and flat-band voltage values were also significantly improved, confirming well interface quality. At higher temperatures (800&#xa0;°C), the emergence of silicate phases, as corroborated by FTIR and XRD analyses, led to a degradation in dielectric integrity and increased trap formation. Structural and surface analyses supported these findings, with increased crystallinity and moderate roughness contributing to electrical behavior. Notably, the incorporation of a thin SiO<sub>2</sub> interfacial layer played a pivotal role in suppressing interface states and stabilizing the oxide–semiconductor boundary. The results demonstrate that precise thermal engineering of Sc<sub>2</sub>O<sub>3</sub> dielectrics enables substantial performance gains, positioning this structure as a strong candidate for future high-κ MOS technologies.</p>

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Tuning electrical performance of Sc2O3/SiO2/Si MOS capacitors through interface and thermal processing

  • 期刊论文

  • 发表日期：

    2025年12月12日

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  • Muhsin Uğur Doğan

摘要

In this work, a systematic investigation is conducted on the electrical characteristics and interface engineering of metal–oxide–semiconductor (MOS) capacitors employing a novel Sc2O3/SiO₂ gate dielectric stack. Emphasis is placed on elucidating the critical roles of post-deposition annealing processes and the interfacial SiO₂ layer in modulating the interfacial quality and overall device performance. Detailed capacitance–voltage (C–V) and conductance–voltage (G–V) analyses demonstrated a marked improvement in critical electrical parameters, most notably a significant reduction in effective oxide charge (Neff ≈ 2.5 × 101⁰ cm⁻2) and interface trap density (Dit ≈ 5.3 × 101⁰ cm⁻2) following annealing at 600 °C, underscoring effective defect passivation. Barrier height and flat-band voltage values were also significantly improved, confirming well interface quality. At higher temperatures (800 °C), the emergence of silicate phases, as corroborated by FTIR and XRD analyses, led to a degradation in dielectric integrity and increased trap formation. Structural and surface analyses supported these findings, with increased crystallinity and moderate roughness contributing to electrical behavior. Notably, the incorporation of a thin SiO2 interfacial layer played a pivotal role in suppressing interface states and stabilizing the oxide–semiconductor boundary. The results demonstrate that precise thermal engineering of Sc2O3 dielectrics enables substantial performance gains, positioning this structure as a strong candidate for future high-κ MOS technologies.