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<p>This study presents a detailed experimental investigation of temperature-dependent electrical properties of normally-off horizontally aligned triangular-shaped gallium nitride (GaN) nanowire wrap-gate transistor in the temperature range of 100–300&#xa0;K in steps of 50&#xa0;K. By employing advanced nanofabrication techniques and state-of-the-art measurement protocols, the temperature-dependent electrical characteristics including drain current (I<sub>ds</sub>) versus gate voltage (V<sub>gs</sub>) and transconductance(g<sub>m</sub>) versus gate voltage (V<sub>gs</sub>) have been systematically evaluated. It is observed that the experimental values of drain current increase with increasing temperature for lower bias regimes (i.e., V<sub>gs</sub> &lt; 2&#xa0;V) , whereas drain current decreases with increasing temperature for higher bias regimes (i.e., V<sub>gs</sub> &gt; 2&#xa0;V). Our results not only elucidate the interplay between temperature-dependent characteristics and normally-off characteristics in horizontally aligned triangular-shaped GaN nanowires but also provide a robust framework for future design strategies aimed at optimizing high-performance semiconductor devices in extreme miniaturization regimes.</p>

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Temperature-dependent electrical characteristics of normally-off triangular-shaped GaN nanowire wrap-gate transistors

  • 期刊论文

  • 发表日期：

    2025年9月28日

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  • Ki-Sik Im,
  • Peddathimula Puneetha,
  • Yeo Jin Choi,
  • Manal Zafar,
  • Chanyeong Park,
  • Seunghwan Jang,
  • Dong Yeon Lee,
  • Sung Jin An,
  • Siva Pratap Reddy Mallem

摘要

This study presents a detailed experimental investigation of temperature-dependent electrical properties of normally-off horizontally aligned triangular-shaped gallium nitride (GaN) nanowire wrap-gate transistor in the temperature range of 100–300 K in steps of 50 K. By employing advanced nanofabrication techniques and state-of-the-art measurement protocols, the temperature-dependent electrical characteristics including drain current (Ids) versus gate voltage (Vgs) and transconductance(gm) versus gate voltage (Vgs) have been systematically evaluated. It is observed that the experimental values of drain current increase with increasing temperature for lower bias regimes (i.e., Vgs < 2 V) , whereas drain current decreases with increasing temperature for higher bias regimes (i.e., Vgs > 2 V). Our results not only elucidate the interplay between temperature-dependent characteristics and normally-off characteristics in horizontally aligned triangular-shaped GaN nanowires but also provide a robust framework for future design strategies aimed at optimizing high-performance semiconductor devices in extreme miniaturization regimes.