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<p>This study investigates the structural and electrical properties of Al/(Sc₂O₃/SiO₂/4H-SiC)/Ag MOS capacitors, focusing on the effects of the annealing temperature on the performance metrics. Sc₂O₃ films were deposited via electron beam deposition, while SiO₂ was grown through dry oxidation. The optimal annealing temperature was determined, alongside an analysis of the SiO₂ interfacial layer’s effect on the capacitors’ characteristics. Key findings reveal that increased annealing temperatures enhance the capacitance–voltage (C-V) and conductance-voltage (G-V) measurements. Specifically, capacitance (C<sub>c</sub>) and conductance (G<sub>c</sub>) significantly improved for the S-800 sample, reflecting enhanced interface quality and effective oxide state density (N<sub>eff</sub>), which increased with temperature, peaking at 800&#xa0;°C. Crystallite sizes varied from 249&#xa0;Å to 309&#xa0;Å, with lattice parameters and dislocation density exhibiting trends reflective of temperature increases, although anomalies were observed at 1000&#xa0;°C. While series resistance (R<sub>s</sub>) displayed no clear trend, the interface density of states (D<sub>it</sub>) decreased, and parameters such as donor concentration (N<sub>D</sub>), breakdown electric field maximum (E<sub>m</sub>), and barrier height (φᵦ) diminished with higher annealing temperatures. Overall, the findings underscore annealing as a critical factor for optimizing MOS capacitor functionality, highlighting a balance between structural improvements and electrical performance metrics.</p>

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Characterization of Sc2O3/SiO2/SiC MOS capacitors: role of annealing temperature on microstructural and electrical properties

  • 期刊论文

  • 发表日期：

    2025年9月24日

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  • D. Nziengui,
  • Ş. Kaya,
  • R. Terzioğlu,
  • C. Terzioğlu

摘要

This study investigates the structural and electrical properties of Al/(Sc₂O₃/SiO₂/4H-SiC)/Ag MOS capacitors, focusing on the effects of the annealing temperature on the performance metrics. Sc₂O₃ films were deposited via electron beam deposition, while SiO₂ was grown through dry oxidation. The optimal annealing temperature was determined, alongside an analysis of the SiO₂ interfacial layer’s effect on the capacitors’ characteristics. Key findings reveal that increased annealing temperatures enhance the capacitance–voltage (C-V) and conductance-voltage (G-V) measurements. Specifically, capacitance (Cc) and conductance (Gc) significantly improved for the S-800 sample, reflecting enhanced interface quality and effective oxide state density (Neff), which increased with temperature, peaking at 800 °C. Crystallite sizes varied from 249 Å to 309 Å, with lattice parameters and dislocation density exhibiting trends reflective of temperature increases, although anomalies were observed at 1000 °C. While series resistance (Rs) displayed no clear trend, the interface density of states (Dit) decreased, and parameters such as donor concentration (ND), breakdown electric field maximum (Em), and barrier height (φᵦ) diminished with higher annealing temperatures. Overall, the findings underscore annealing as a critical factor for optimizing MOS capacitor functionality, highlighting a balance between structural improvements and electrical performance metrics.