Scholarlink

<p>Ge and GeSn materials have garnered significant attention due to their high carrier mobility and tunable band structure, making them promising candidates for low-power electronic applications. In this work, a novel ferroelectric junctionless GOI and GeSnOI transistors is presented and characterized. The initial Ge layer or Ge/GeSn structure was grown on Si substrates and later bonded and back-etched. The final layer of Ge and GeSn in (GOI and GeSnOI) with thickness of 50 nm was obtained by wet etching using a spinner tool while etchant agent was dropped carefully to etch uniformly over the Si wafer. Ge preamorphization implantation (PAI) and rapid thermal annealing (RTA) processes were employed to form the NiGe/p-Ge contact, resulting in a contact resistance as low as 0.55 × 10<sup>–8</sup> Ω-cm<sup>2</sup>. In addition, the formed transistors show excellent characteristics. Notably, extracted mobilities of GOI and GeSnOI transistor are in range of 200–400 cm<sup>2</sup>/V·s and 500–600 cm<sup>2</sup>/V·s, respectively. Subthreshold swing (SS) of the ferroelectric transistors on GOI and Ge<sub>0.92</sub>Sn<sub>0.08</sub>OI substrates was measured to be 37.7&#xa0;mV/dec and 43.7&#xa0;mV/dec, respectively. Our work demonstrates a novel and reliable process of Ge-based junctionless transistors for future low-power consumption logic circuits.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Fabrication and characterization of ferroelectric junctionless GOI and GeSnOI transistors for low-power applications

  • 期刊论文

  • 发表日期：

    2025年1月16日

查看全文
  • Yuhui Ren,
  • Jiahan Ke,
  • Hongxiao Lin,
  • Xuewei Zhao,
  • Zhenzhen Kong,
  • Renrong Liang,
  • Jun Xu,
  • Bin Lu,
  • Yuanhao Miao,
  • Henry H. Radamson

摘要

Ge and GeSn materials have garnered significant attention due to their high carrier mobility and tunable band structure, making them promising candidates for low-power electronic applications. In this work, a novel ferroelectric junctionless GOI and GeSnOI transistors is presented and characterized. The initial Ge layer or Ge/GeSn structure was grown on Si substrates and later bonded and back-etched. The final layer of Ge and GeSn in (GOI and GeSnOI) with thickness of 50 nm was obtained by wet etching using a spinner tool while etchant agent was dropped carefully to etch uniformly over the Si wafer. Ge preamorphization implantation (PAI) and rapid thermal annealing (RTA) processes were employed to form the NiGe/p-Ge contact, resulting in a contact resistance as low as 0.55 × 10–8 Ω-cm2. In addition, the formed transistors show excellent characteristics. Notably, extracted mobilities of GOI and GeSnOI transistor are in range of 200–400 cm2/V·s and 500–600 cm2/V·s, respectively. Subthreshold swing (SS) of the ferroelectric transistors on GOI and Ge0.92Sn0.08OI substrates was measured to be 37.7 mV/dec and 43.7 mV/dec, respectively. Our work demonstrates a novel and reliable process of Ge-based junctionless transistors for future low-power consumption logic circuits.