Investigation of impact of floating gate implantation annealing on the characteristics of 4Xnm ETOX NOR-flash memory
摘要
In this letter, the effects of floating gate (FG) implantation annealing for 4Xnm NOR-flash on the memory flash physical structure and electrical characteristics are investigated. The wafer of which FG implantation annealing put before pad nitride deposition suffers bin9 fail issues that result from cell-active area damage. The formation mechanism of surface defects caused by the reversible reaction of solid-state negative SiO2, polysilicon, and gaseous SiO under high temperature and low temperature is investigated in detail. After the process optimization, the surface defects are significantly reduced and the yield rate is greatly improved.